1. Field of the Invention
The present invention relates to a method for analyzing a defect of a semiconductor device, and more particularly to a method for electrically analyzing a defect for a pattern having a latch structure, such as SRAM or a sense amplifier of DRAM.
2. Description of the Prior Art
As generally known in the art, defect analysis for SRAM employs a physical measuring method such as SEM, TEM or the like, or a method in which a test pattern (it may not wholly correspond to a normal pattern) is prepared under the same design rule as that of a normal pattern and the test pattern is analyzed with respect to whether or not a short circuit or a bridge is generated.
However, since a normal pattern and a test pattern (e.g., an SRAM cell and a correspondent test cell) partially differ from each other, it is problematic to exactly find out whether or not the normal pattern the normal pattern is defective simply by defect analysis for the test pattern.